1. Field of the Invention
This invention relates generally to pointers and, more specifically, to a data pointer for generating an indirect addressing mode address within a single cycle for a selected one of a plurality of multiple indirect addressing modes.
2. Description of the Prior Art
Generally speaking, a processor is an entity where a central processing unit (CPU) is present and is used to fetch and execute stored instructions or microcode. Some examples of processors are microcontrollers, microprocessors, and digital signal processors. Each type of processor operates on data which is commonly referred to as operands. This data is generally stored in registers or memory space.
An instruction directs the CPU of a processor to execute a certain operation as well as to identify one or more operand(s) for the operation. Processors offer various means for addressing the data for an operation. These means are commonly referred to as addressing modes. The addressing modes are typically used for arithmetic and logical operations and data move operations and may apply to a source operand, a destination operand, or both.
When implementing certain indirect addressing modes, there are certain speed critical issues which must be addressed. In order to obtain the proper address for certain indirect addressing modes, two or more cycles are required to properly load the correct address. These delays may cause timing problems. For example, if an instruction requires an indirect addressing mode with offset, the value needs to be available immediately. If one tries to perform the offset function after the request, it could not be done with a simple serial adder. A look ahead adder may be able to provide the proper address, but implementing this type of adder would require large amounts of valuable silicon real estate thereby increasing the cost. Therefore, there must either be a tradeoff between silicon real estate or timing in the prior art.
Therefore, a need existed to provide a data pointer for generating indirect addressing mode addresses. The data pointer must be able to generate the indirect addressing mode address within a single cycle for the selected indirect addressing mode. The data pointer must be able to generate the indirect addressing mode address within a single cycle for the selected indirect addressing mode without significantly increasing the amount of silicon real estate in the processor architecture.